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cy7c1354dv25, cy7c1356dv25 9-mbit (256k x 36/512k x 18) pipelined sram with nobl? architecture cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-48974 rev. *b revised march 20, 2010 features pin compatible with and functionally equivalent to zbt? supports 250 mhz bus operations with zero wait states available speed grades are 250, 200, and 166 mhz internally self timed output buffer control to eliminate the need to use asynchronous oe fully registered (inputs and outputs) for pipelined operation byte write capability single 2.5v power supply (v dd ) fast clock-to-output times ? 2.8 ns (for 250 mhz device) clock enable (cen ) pin to suspend operation synchronous self timed writes available in pb-free 100-pin tqfp package, pb-free and non pb-free 119-ball bga package, and 165-ball fbga package ieee 1149.1 jtag comp atible boundary scan burst capability?linear or interleaved burst order ?zz? sleep mode and stop clock options functional description the cy7c1354dv25 and cy7c1356dv25 are 2.5v, 256k x 36 and 512k x 18 synchronous pipelined burst srams with no bus latency? (nobl ?) logic, respectively. they are designed to support unlimited true back to back read and write operations with no wait states. the cy7c1354dv25 and cy7c1356dv25 are equipped with the advanced (nobl) logic required to enable consecutive read and write operat ions with data being trans- ferred on every clock cycle. this feature dramatically improves the throughput of data in system s that require frequent write and read transitions. the cy7c1354dv25 and cy7c1356dv25 are pin compatible with and functionally equivalent to zbt devices. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation an d extends the previous clock cycle. write operations are controll ed by the byte write selects (bw a ?bw d for cy7c1354dv25 and bw a ?bw b for cy7c1356dv25) and a write enable (we ) input. all writes are conducted with on-chip synchronous self timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide easy bank selection and output tri-state control. to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. for best practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com . selection guide description 250 mhz 200 mhz 166 mhz unit maximum access time 2.8 3.2 3.5 ns maximum operating current 250 220 180 ma maximum cmos standby current 40 40 40 ma [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 2 of 30 logic block diagram ? cy7c1354dv25 ( 256k x 36) a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dq s dq p a dq p b dq p c dq p d d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s e clk cen write drivers bw c bw d zz sleep control o u t p u t r e g i s t e r s [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 3 of 30 logic block diagram ? cy7c1356dv25 ( 512k x 18 ) a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dq s dq p a dq p b d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e clk cen write drivers zz sleep control [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 4 of 30 contents features ............................................................................. 1 functional description ..................................................... 1 selection guide ................................................................ 1 logic block diagram ? cy7c1354dv25 (256k x 36) ..... 2 logic block diagram ? cy7c1356dv25 (512k x 18) ..... 3 pin configuration ............................................................. 6 100-pin tqfp pinout .................................................. 6 pin definitions .................................................................. 9 functional overview ...................................................... 10 single read accesses .............................................. 10 burst read accesses ................................................ 10 single write accesses ............................................... 11 burst write accesses ................................................ 11 sleep mode ............................................................... 11 interleaved burst address table (mode = floating or vdd) ............................................. 11 linear burst address table (mode = gnd) ................ 11 zz mode electrical characteristics ............................... 11 truth table ...................................................................... 12 write cycle description ................................................. 12 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 13 disabling the jtag feature ...................................... 13 test access port (tap) ............................................. 14 performing a tap r eset .......... .............. .......... 14 tap registers ...................................................... 14 tap instruction set ................................................... 15 tap timing ...................................................................... 16 tap ac switching characteristics ............................... 16 2.5v tap ac test conditions ........................................ 17 tap dc electrical characteristics and operating condi- tions ................................................................................. 17 identification register definitions ................................ 17 scan register sizes ....................................................... 17 identification codes ....................................................... 18 boundary scan exit order (256k 36) ..................... 19 boundary scan exit order (512k 18) ..................... 20 maximum ratings ........................................................... 21 operating range ............................................................. 21 electrical characteristics ............................................... 21 capacitance [15] ................................................................ 22 thermal resistance [15] ................................................... 22 switching characteristics .............................................. 23 switching waveforms .................................................... 24 ordering information ...................................................... 27 package diagrams .......................................................... 28 document history page ................................................. 31 sales, solutions, and legal information ...................... 31 worldwide sales and design s upport ......... .............. 31 products .................................................................... 31 psoc solutions ......................................................... 31 [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 5 of 30 pin configuration the pin configuration for cy7c1354dv25 and cy7c1356dv25 follow. 100-pin tqfp pinout a a a a a 1 a 0 v ss v dd a a a a a a v ddq v ss dqb dqb dqb v ss v ddq dqb dqb v ss nc v dd dqa dqa v ddq v ss dqa dqa v ss v ddq v ddq v ss dqc dqc v ss v ddq dqc v dd v ss dqd dqd v ddq v ss dqd dqd dqd v ss v ddq a a ce 1 ce 2 bwa ce 3 v dd v ss clk we cen oe nc(18m) a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz cy7c1354dv25 a a a a a 1 a 0 v ss v dd a a a a a a a nc nc v ddq v ss nc dqpa dqa dqa v ss v ddq dqa dqa v ss nc v dd dqa dqa v ddq v ss dqa dqa nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dqb dqb v ss v ddq dqb dqb v dd v ss dqb dqb v ddq v ss dqb dqb dqpb nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bwb bwa ce 3 v dd v ss clk we cen oe nc(18m) a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode cy7c1356dv25 bwd mode bwc dqc dqc dqc dqc dqpc dqd dqd dqd dqpb dqb dqa dqa dqa dqa dqpa dqb dqb (256k 36) (512k 18) bwb nc nc nc dqc nc nc(288m) nc(144m) nc(72m) nc(36m) nc(288m) nc(144m) nc(72m) nc(36m) dqpd [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 6 of 30 119-ball bga pinout cy7c1354dv25 (256k x 36) 1 2 3 4 5 6 7 a v ddq aanc/18maav ddq b nc/576m ce 2 aadv/ld ace 3 nc c nc/1g a a v dd aanc d dq c dqp c v ss nc v ss dqp b dq b e dq c dq c v ss ce 1 v ss dq b dq b f v ddq dq c v ss oe v ss dq b v ddq g dq c dq c bw c abw b dq b dq b h dq c dq c v ss we v ss dq b dq b j v ddq v dd nc v dd nc v dd v ddq k dq d dq d v ss clk v ss dq a dq a l dq d dq d bw d nc bw a dq a dq a m v ddq dq d v ss cen v ss dq a v ddq n dq d dq d v ss a1 v ss dq a dq a p dq d dqp d v ss a0 v ss dqp a dq a r nc/144m a mode v dd nc a nc/288m t nc nc/72m a a a nc/36m zz u v ddq tms tdi tck tdo nc v ddq 119-ball bga pinout cy7c1356dv25 (512k x 18) 1 2 3 4 5 6 7 a v ddq aanc/18maav ddq b nc/576m ce 2 aadv/ld ace 3 nc c nc/1g a a v dd aanc d dq b nc v ss nc v ss dqp a nc e nc dq b v ss ce 1 v ss nc dq a f v ddq nc v ss oe v ss dq a v ddq g nc dq b bw b av ss nc dq a h dq b nc v ss we v ss dq a nc j v ddq v dd nc v dd nc v dd v ddq k nc dq b v ss clk v ss nc dq a l dq b nc v ss nc bw a dq a nc m v ddq dq b v ss cen v ss nc v ddq n dq b nc v ss a1 v ss dq a nc p nc dqp b v ss a0 v ss nc dq a r nc/144m a mode v dd nc a nc/288m t nc/72m a a nc/36m a a zz u v ddq tms tdi tck tdo nc v ddq pin configuration (continued) the pin configuration for cy7c1354dv25 and cy7c1356dv25 follow. [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 7 of 30 165-ball fbga pinout cy7c1354dv25 (256k x 36) 1 2 3 4 5 6 7 8 9 10 11 a nc/576m a ce 1 bw c bw b ce 3 cen adv/ld aanc b nc/1g a ce 2 bw d bw a clk we oe nc/18m a nc c dqp c nc v ddq v ss v ss v ss v ss v ss v ddq nc dqp b d dq c dq c v ddq v dd v ss v ss v ss v dd v ddq dq b dq b e dq c dq c v ddq v dd v ss v ss v ss v dd v ddq dq b dq b f dq c dq c v ddq v dd v ss v ss v ss v dd v ddq dq b dq b g dq c dq c v ddq v dd v ss v ss v ss v dd v ddq dq b dq b h nc nc nc v dd v ss v ss v ss v dd nc nc zz j dq d dq d v ddq v dd v ss v ss v ss v dd v ddq dq a dq a k dq d dq d v ddq v dd v ss v ss v ss v dd v ddq dq a dq a l dq d dq d v ddq v dd v ss v ss v ss v dd v ddq dq a dq a m dq d dq d v ddq v dd v ss v ss v ss v dd v ddq dq a dq a n dqp d nc v ddq v ss nc nc nc v ss v ddq nc dqp a p nc/144m nc/72m a a tdi a1 tdo a a a nc/288m r modenc/36maatmsa0tckaaaa 165-ball fbga pinout cy7c1356dv25 (512k x 18) 1 2 3 4 5 6 7 8 9 10 11 a nc/576m a ce 1 bw b nc ce 3 cen adv/ld aaa b nc/1g a ce 2 nc bw a clk we oe nc/18m a nc c nc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqp a d nc dq b v ddq v dd v ss v ss v ss v dd v ddq nc dq a e nc dq b v ddq v dd v ss v ss v ss v dd v ddq nc dq a f nc dq b v ddq v dd v ss v ss v ss v dd v ddq nc dq a g nc dq b v ddq v dd v ss v ss v ss v dd v ddq nc dq a h nc nc nc v dd v ss v ss v ss v dd nc nc zz j dq b nc v ddq v dd v ss v ss v ss v dd v ddq dq a nc k dq b nc v ddq v dd v ss v ss v ss v dd v ddq dq a nc l dq b nc v ddq v dd v ss v ss v ss v dd v ddq dq a nc m dq b nc v ddq v dd v ss v ss v ss v dd v ddq dq a nc n dqp b nc v ddq v ss nc nc nc v ss v ddq nc nc p nc/144m nc/72m a a tdi a1 tdo a a a nc/288m r modenc/36maatmsa0tckaaaa pin configuration (continued) the pin configuration for cy7c1354dv25 and cy7c1356dv25 follow. [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 8 of 30 pin definitions pin name io pin description a0 a1 a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. bw a, bw b, bw c, bw d, input- synchronous byte write select inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bw a controls dq a and dqp a , bw b controls dq b and dqp b , bw c controls dq c and dqp c , bw d controls dq d and dqp d . we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance or load input used to advance the on-chip address counter or load a new address . when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input- clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select and deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select and deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select and deselect the device. oe input- asynchronous output enable, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pi ns are allowed to behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging fr om a deselected state and when the device is deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. because deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. dq s i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip da ta register that is triggered by the rising edge of clk. as outputs, t hey deliver the data contained in the memory location specified by addresses during the previous clock rise of the read cy cle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq a ?dq d are placed in a tri-state condition. the outpu ts are automatically tr i-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regar dless of the state of oe . dqp x i/o- synchronous bidirectional data parity i/o lines . functionally, these signals are identical to dq [a:d]. during write sequences, dqp a is controlled by bw a , dqp b is controlled by bw b , dqp c is controlled by bw c , and dqp d is controlled by bw d . mode input strap pin mode input . selects the burst order of the device. tied high selects the interleaved burst order. pulled low selects the linear burst order. mode should not change states during operation. when left floating mode is default high, to an interleaved burst order. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 9 of 30 functional overview the cy7c1354dv25 and cy7c1356dv25 are synchronous pipelined burst nobl srams designed specifically to eliminate wait states during write/read tran sitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous opera- tions are qualified with cen . all data outputs pass through output registers controlled by the ri sing edge of the clock. maximum access delay from the clock rise (t co ) is 2.8 ns (250 mhz device). accesses are initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device is latched. the access can either be a read or write operation, depend ing on the status of the write enable (we ). bw [d:a] can be used to conduct byte write opera- tions. write operations are qualif ied by the write enable (we ). all writes are simplified with on-chip synchronous self timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and de selects) are pipelined. adv/ld must be driven low when the device is deselected to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. at the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.8 ns (250 mhz device) provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low for the device to drive out the requested data. during the second clock, a subsequent operation (read, write, and deselect ) is initiated. deselecting the device is also pipelined. therefore, when the sram is deselected at clock rise by one of the chip enable signals, its output tri-states following the next clock rise. burst read accesses the cy7c1354dv25 and cy7c1356dv25 have an on-chip burst counter that provides the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low to load a new address into the sram, as described in the single read accesses section. the sequence of the burst coun ter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in t he burst sequence, and wraps around when incremented sufficiently. a high input on adv/ld increments the internal burst count er regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. tms test mode select synchronous controls the test access port state machine . sampled on the rising edge of tck. tck jtag-clock clock input to th e jtag circuitry . v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device . should be connected to ground of the system. nc ? no connects . this pin is not connected to the die. nc (18, 36, 72, 144, 288, 576, 1g ? these pins are not connected . they will be used for expansion to the 18m, 36m, 72m, 144m 288m, 576m, and 1g densities. zz input- asynchronous zz ?sleep? input . this active high input places the device in a non-time critical ?sleep? condition with data integrity preserved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. pin definitions (continued) pin name io pin description [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 10 of 30 single write accesses write access are initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to a 0 a 16 is loaded into the address register. the write signals are latched into the control logic block. on the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dq and dqp (dq a,b,c,d /dqp a,b,c,d for cy7c1354dv25 and dq a,b /dqp a,b for cy7c1356dv25). in addition, the address for the subsequent access (read, write, and deselec t) is latched into the address register (provided the appropriat e control signals are asserted). on the next clock rise the data presented to dq and dqp (dq a,b,c,d /dqp a,b,c,d for cy7c1354dv25 and dq a,b /dqp a,b for cy7c1356dv25) (or a subset for byte write operations, see write cycle description tables for details) inputs is latched into the device and the write is complete. the data written during the writ e operation is controlled by bw (bw a,b,c,d for cy7c1354dv25 and bw a,b for cy7c1356dv25) signals. the cy7c1354dv25/cy7c1356dv25 provides byte write capability that is described in the write cycle description tables. asserting the write enable input (we ) with the selected byte write select (bw ) input selectively writes to only the desired bytes. bytes not selected during a byte write operation remains unaltered. a synchronous self timed write mechanism is provided to simplify the write ope rations. byte write capability is included to greatly simplify read, modify, and write sequences, which can be reduced to simple byte write operations. because the cy7c1354dv25 and cy7c1356dv25 are common i/o devices, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dq and dqp (dq a,b,c,d /dqp a,b,c,d for cy7c1354dv25 and dq a,b /dqp a,b for cy7c1356dv25) inputs. doing so tri-states the output drivers. as a safety precaution, dq and dqp (dq a,b,c,d /dqp a,b,c,d for cy7c1354dv25 and dq a,b /dqp a,b for cy7c1356dv25) are automatically tri-stated during th e data portion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1354dv25 and cy7c1356dv25 has an on-chip burst counter that provides the ability to supply a single address and conduct up to four write oper ations without reasserting the address inputs. adv/ld must be driven low to load the initial address, as described in the single write access section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bw (bw a,b,c,d for cy7c1354dv25 and bw a,b for cy7c1356dv25) inputs must be driven in each cycle of the burst write to write th e correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. when in this mode, data int egrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3, must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address second address third address fourth address a1,a0 a1,a0 a1,a0 a1,a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address second address third address fourth address a1,a0 a1,a0 a1,a0 a1,a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? 0.2v 50 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current this parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 11 of 30 truth table the truth table for cy7c1354dv25 and cy7c1356dv25 follows. [1, 2, 3, 4, 5, 6, 7] operation address used ce zz adv/ ld we bwx oe cen clk dq deselect cycle none h l l x x x l l-h tri-state continue deselect cycle none x l h x x x l l-h tri-state read cycle (begin burst) exte rnal l l l h x l l l-h data out (q) read cycle (continue burst) next x l h x x l l l-h data out (q) nop/dummy read (begin burst) external l l l h x h l l-h tri-state dummy read (continue burst) next x l h x x h l l-h tri-state write cycle (begin burst) external l l l l l x l l-h data in (d) write cycle (continue burst) next x l h x l x l l-h data in (d) nop/write abort (begin burs t) none l l l l h x l l-h tri-state write abort (continue burst) next x l h x h x l l-h tri-state ignore clock edge (stall) current x l x x x x h l-h ? sleep mode none x h x x x x x x tri-state write cycle description write cycle description for cy7c1354dv25 follows. [1, 2, 3, 8] function we bw d bw c bw b bw a read h x x x x write ?no bytes written l h h h h write byte a? (dq a and dqp a) lhhhl write byte b ? (dq b and dqp b) lhhlh write bytes b, a l h h l l write byte c ? (dq c and dqp c) lhlhh write bytes c, a l h l h l write bytes c, b l h l l h write bytes c, b, a l h l l l write byte d ? (dq d and dqp d) llhhh write bytes d, a l l h h l write bytes d, b l l h l h write bytes d, b, a l l h l l write bytes d, c l l l h h write bytes d, c, a l l l h l write bytes d, c, b l l l l h write all bytes l l l l l notes 1. x = ?don?t care?, h = logic high, l = logic low, ce stands for all chip enables active. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see write cycle description tables for details. 2. write is defined by we and bw x . see write cycle description tablse for details. 3. when a write cycle is detected, all i/os are tri-stated, even during byte writes. 4. the dq and dqp pins are controlled by the current cycle and the oe signal. 5. cen = h inserts wait states. 6. device will power-up deselected and the i/os in a tri-state condition, regardless of oe . 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dqs a nd dqp x = tri-state when oe is inactive or when the device is deselected, and dqs = data when oe is active. [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 12 of 30 ieee 1149.1 serial boundary scan (jtag) the cy7c1354dv25 and cy7c1356dv25 incorporates a serial boundary scan test access port (tap) in the bga package only. the tqfp package does not offer this functionality. this part operates in accordance with ieee standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standar d 2.5v i/o logic levels. the cy7c1354dv25 and cy7c1356dv25 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. during power up, the device comes up in a reset state which does not interfere with the operation of the device. write cycle description for cy7c1356dv25 follows. [1, 2, 3, 8] function we bw b bw a read hx x write ? no bytes written l h h write byte a ? (dq a and dqp a) lhl write byte b ? (dq b and dqp b) llh write both bytes l l l notes 8. table only lists a partial listing of the by te write combinations. any combination of bw x is valid. appropriate write will be done based on which byte write is active. 9. the 0/1 next to each state represents the value of tms at the rising edge of the tck. figure 1. tap controller state diagram [9] test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 13 of 30 test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck.test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see figure 1 . tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. (see figure 2 .) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see figure 1 .) performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. during power up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected betw een the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in tap controller block diagram . during power up, the instructio n register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the by pass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is loaded with the contents of the ram i/o ring when the tap controll er is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in the identification register definitions table. figure 2. tap controller block diagram bypass register 0 instruction register 0 1 2 identication register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry selection circuitry tck t ms tap controller tdi td o [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 14 of 30 tap instruction set overview eight different instructions are possible with the three bit instruction register. all combinations are listed in the identifi- cation codes table. three of these instructions are listed as reserved and should not be used. the other five instructions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction after it is shifte d in, the tap controller must be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loade d into the instruction register during power up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z stat e until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that t he tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transition. the tap may then tr y to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap cont roller's capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all othe r signals and simply ignore the value of the ck and ck# captured in the boundary scan register. when the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boun dary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when require d?that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system ou tput pins. this inst ruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 15 of 30 tap timing figure 3 shows the tap timings. figure 3. tap timing and test conditions tap ac switching characteristics over the operating range [10, 11] parameter description min max unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 20 ns t tl tck clock low time 20 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns setup times t tmss tms setup to tck clock rise 5 ns t tdis tdi setup to tck clock rise 5 ns t cs capture setup to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns notes 10. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. test conditions are specified using t he load in tap ac test conditions. t r /t f = 1 ns. t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 16 of 30 2.5v tap ac test conditions input pulse levels ................................................v ss to 2.5v input rise and fall time ....................................................1 ns input timing reference levels .. ...................................... 1.25v output reference levels ............................................... 1.25v test load termination supply vo ltage .................... ........1.25v figure 4. 2.5v tap ac output load equivalent t do 1.25v 20p f z=50 ? o 50 ? (0c < ta < +70c; vdd = 2.5v 0.125v unless otherwise noted) [12] parameter description test conditions min max unit v oh1 output high voltage i oh = ?1.0 ma, v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a,v ddq = 2.5v 2.1 v v ol1 output low voltage i ol = 8.0 ma, v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 2.5v 0.2 v v ih input high voltage v ddq = 2.5v 1.7 v dd + 0.3 v v il input low voltage v ddq = 2.5v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a identification register definitions instruction field cy7c1354dv25 cy7c1356dv25 description revision number (31:29) 000 000 reserved for version number. cypress device id (28:12) 01011001000100110 01011001000010110 reserved for future use. cypress jedec id (11:1) 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 indicate the presence of an id register. scan register sizes register name bit size (x36) bit size (x18) instruction 3 3 bypass 1 1 id 32 32 boundary scan order (119-ball bga package) 69 69 boundary scan order (165-ball fbga package) 69 69 note: 12. all voltages referenced to v ss (gnd). [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 17 of 30 identification codes instruction code description extest 000 captures the input /output ring contents. places the boundary scan register between the tdi and tdo. forces all sram outputs to high-z state. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the i nput/output contents. places the boundary sc an register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instru ction is reserved for future use. sample/preload 100 captures th e input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instru ction is reserved for future use. reserved 110 do not use: this instru ction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 18 of 30 boundary scan exit order (256k 36) bit # 119-ball id 165-ball id 1k4b6 2h4b7 3m4a7 4f4b8 5b4a8 6g4a9 7c3b10 8b3a10 9d6c11 10 h7 e10 11 g6 f10 12 e6 g10 13 d7 d10 14 e7 d11 15 f6 e11 16 g7 f11 17 h6 g11 18 t7 h11 19 k7 j10 20 l6 k10 21 n6 l10 22 p7 m10 23 n7 j11 24 m6 k11 25 l7 l11 26 k6 m11 27 p6 n11 28 t4 r11 29 a3 r10 30 c5 p10 31 b5 r9 32 a5 p9 33 c6 r8 34 a6 p8 35 p4 r6 36 n4 p6 37 r6 r4 38 t5 p4 39 t3 r3 40 r2 p3 41 r3 r1 42 p2 n1 43 p1 l2 44 l2 k2 45 k1 j2 46 n2 m2 47 n1 m1 48 m2 l1 49 l1 k1 50 k2 j1 51 not bonded (preset to 1) not bonded (preset to 1) 52 h1 g2 53 g2 f2 54 e2 e2 55 d1 d2 56 h2 g1 57 g1 f1 58 f2 e1 59 e1 d1 60 d2 c1 61 c2 b2 62 a2 a2 63 e4 a3 64 b2 b3 65 l3 b4 66 g3 a4 67 g5 a5 68 l5 b5 69 b6 a6 boundary scan exit order (256k 36) (continued) bit # 119-ball id 165-ball id [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 19 of 30 boundary scan exit order (512k 18) bit # 119-ball id 165-ball id 1k4b6 2h4b7 3m4a7 4f4b8 5b4a8 6g4a9 7c3b10 8b3a10 9t2a11 10 not bonded (preset to 0) not bonded (preset to 0) 11 not bonded (preset to 0) not bonded (preset to 0) 12 not bonded (preset to 0) not bonded (preset to 0) 13 d6 c11 14 e7 d11 15 f6 e11 16 g7 f11 17 h6 g11 18 t7 h11 19 k7 j10 20 l6 k10 21 n6 l10 22 p7 m10 23 not bonded (preset to 0) not bonded (preset to 0) 24 not bonded (preset to 0) not bonded (preset to 0) 25 not bonded (preset to 0) not bonded (preset to 0) 26 not bonded (preset to 0) not bonded (preset to 0) 27 not bonded (preset to 0) not bonded (preset to 0) 28 t6 r11 29 a3 r10 30 c5 p10 31 b5 r9 32 a5 p9 33 c6 r8 34 a6 p8 35 p4 r6 36 n4 p6 37 r6 r4 38 t5 p4 39 t3 r3 40 r2 p3 41 r3 r1 42 not bonded (preset to 0) not bonded (preset to 0) 43 not bonded (preset to 0) not bonded (preset to 0) 44 not bonded (preset to 0) not bonded (preset to 0) 45 not bonded (preset to 0) not bonded (preset to 0) 46 p2 n1 47 n1 m1 48 m2 l1 49 l1 k1 50 k2 j1 51 not bonded (preset to 1) not bonded (preset to 1) 52 h1 g2 53 g2 f2 54 e2 e2 55 d1 d2 56 not bonded (preset to 0) not bonded (preset to 0) 57 not bonded (preset to 0) not bonded (preset to 0) 58 not bonded (preset to 0) not bonded (preset to 0) 59 not bonded (preset to 0) not bonded (preset to 0) 60 not bonded (preset to 0) not bonded (preset to 0) 61 c2 b2 62 a2 a2 63 e4 a3 64 b2 b3 65 not bonded (preset to 0 not bonded (preset to 0) 66 g3 not bonded (preset to 0) 67 not bonded (preset to 0 a4 68 l5 b5 69 b6 a6 69 b6 a6 69 b6 a6 68 l5 b5 69 b6 a6 66 g3 not bonded (preset to 0) 67 not bonded (preset to 0 a4 68 l5 b5 69 b6 a6 boundary scan exit order (512k 18) (continued) bit # 119-ball id 165-ball id [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 20 of 30 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................ .............. ... ?65c to +150c ambient temperature with power applied ............ ............... .............. ... ?55c to +125c supply voltage on v dd relative to gnd ........?0.5v to +3.6v supply voltage on v ddq relative to gn d ...... ?0.5v to +v dd dc to outputs in tri-state....................?0.5v to v ddq + 0.5v dc input voltage ................................... ?0.5v to v dd + 0.5v current into outputs (low)..... .................................... 20 ma static discharge voltage....... ........... ............ ............ > 2001v (per mil-std-883, method 3015) latch up current ................................................... > 200 ma operating range range ambient temperature v dd / v ddq commercial 0c to +70c 2.5v 5% industrial ?40c to +85c electrical characteristics over the operating range [13, 14] parameter description test conditions min max unit v dd power supply voltage 2.375 2.625 v v ddq i/o supply voltage for 2.5v i/o 2.375 v dd v v oh output high voltage for 2.5v i/o, i oh = ? 1.0 ma 2.0 v v ol output low voltage for 2.5v i/o, i ol = 1.0 ma 0.4 v v ih input high voltage for 2.5v i/o 1.7 v dd + 0.3v v v il input low voltage [13] for 2.5v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 4 ns cycle, 250 mhz 250 ma 5 ns cycle, 200 mhz 220 ma 6 ns cycle, 166 mhz 180 ma i sb1 automatic ce power down current?ttl inputs max v dd , device deselected, v in v ih or v in v il , f = f max = 1/t cyc 4 ns cycle, 250 mhz 130 ma 5 ns cycle, 200 mhz 120 ma 6 ns cycle, 166 mhz 110 ma i sb2 automatic ce power down current?cmos inputs max v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speed grades 40 ma i sb3 automatic ce power down current?cmos inputs max v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = f max = 1/t cyc 4 ns cycle, 250 mhz 120 ma 5 ns cycle, 200 mhz 110 ma 6 ns cycle, 166 mhz 100 ma i sb4 automatic ce power down current?ttl inputs max v dd , device deselected, v in v ih or v in v il , f = 0 all speed grades 40 ma notes 13. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac)> ?2v (pulse width less than t cyc /2). 14. t power-up : assumes a linear ramp from 0v to v dd (minimum) within 200 ms. during this time v ih < v dd and v ddq < v dd . [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 21 of 30 capacitance [15] parameter description test conditions 100 tqfp max 119 bga max 165 fbga max unit c in input capacitance t a = 25c, f = 1 mhz, v dd = 2.5v, v ddq = 2.5v 555pf c clk clock input capacitance 5 5 5 pf c i/o input/output capacitance 5 7 7 pf thermal resistance [15] parameters description test conditions 100 tqfp package 119 bga package 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 29.41 34.1 16.8 c/w jc thermal resistance (junction to case) 6.13 14 3.0 c/w figure 5. ac test loads and waveforms output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 2.5v i/o test load note 15. tested initially and after any design or process change that may affect these parameters. [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 22 of 30 switching characteristics over the operating range [17, 18] parameter description ?250 ?200 ?166 unit min max min max min max t power [16] v cc (typical) to the first access read or write 1 1 1 ms clock t cyc clock cycle time 4.0 5 6 ns f max maximum operating frequency 250 200 166 mhz t ch clock high 1.8 2.0 2.4 ns t cl clock low 1.8 2.0 2.4 ns output times t co data output valid after clk rise 2.8 3.2 3.5 ns t eov oe low to output valid 2.8 3.2 3.5 ns t doh data output hold after clk rise 1.25 1.5 1.5 ns t chz clock to high-z [19, 20, 21] 1.25 2.8 1.5 3.2 1.5 3.5 ns t clz clock to low-z [19, 20, 21] 1.25 1.5 1.5 ns t eohz oe high to output high-z [19, 20, 21] 2.8 3.2 3.5 ns t eolz oe low to output low-z [19, 20, 21] 000ns setup times t as address setup before clk rise 1.4 1.5 1.5 ns t ds data input setup before clk rise 1.4 1.5 1.5 ns t cens cen setup before clk rise 1.4 1.5 1.5 ns t wes we , bw x setup before clk rise 1.4 1.5 1.5 ns t als adv/ld setup before clk rise 1.4 1.5 1.5 ns t ces chip select setup 1.4 1.5 1.5 ns hold times t ah address hold after clk rise 0.4 0.5 0.5 ns t dh data input hold after clk rise 0.4 0.5 0.5 ns t cenh cen hold after clk rise 0.4 0.5 0.5 ns t weh we , bw x hold after clk rise 0.4 0.5 0.5 ns t alh adv/ld hold after clk rise 0.4 0.5 0.5 ns t ceh chip select hold after clk rise 0.4 0.5 0.5 ns notes 16. this part has a voltage regulator internally; t power is the time power needs to be supplied above v dd minimum initially, before a read or write operation can be initiated. 17. timing reference level is when v ddq = 2.5v. 18. test conditions shown in (a) of ac test loads unless otherwise noted. 19. t chz , t clz , t eolz , and t eohz are specified with ac test conditions shown in (b) of ac test loads. transition is measured 200 mv from steady-state voltage . 20. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condit ion, but reflect parameters guar anteed over worst case user condi tions. device is designed to achieve high-z prior to low-z under the same system conditions. 21. this parameter is sampled and not 100% tested. [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 23 of 30 switching waveforms figure 6. read/write timing [22, 23, 24] notes 22. for this waveform zz is tied low. 23. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high,ce 1 is high or ce 2 is low or ce 3 is high. 24. order of the burst sequence is determined by the status of t he mode (0 = linear, 1 = interleaved). burst operations are opti onal. write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds data i n-out (dq) t clz d(a1) d(a2) d(a5) q(a4) q(a3) d(a2+1) t doh t chz t co write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz t doh dont care undefined q(a6) q(a4+1) [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 24 of 30 figure 7. nop, st all and deselect cycles [22, 23, 25] note 25. the ignore clock edge or stall cycle (clock 3) illustrated cen being used to create a pause. a wr ite is not perform ed during this cycle. switching waveforms (continued) read q(a3) 456 78910 clk ce we cen bw x adv/ld address a3 a4 a5 d(a4) data in-out (dq) a1 q(a5) write d(a4) stall write d(a1) 123 read q(a2) stall nop read q(a5) deselect continue deselect don?t care undefined t chz a2 d(a1) q(a2) q(a3) [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 25 of 30 figure 8. zz mode timing [26, 27] switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 26. device must be deselected when entering zz mode. see write cycle description tables for all possible signal conditions to deselect the device. 27. i/os are in high-z when exiting zz sleep mode. [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 26 of 30 ordering information cypress offers other versions of this ty pe of product in many different configurat ions and features. the following table contai ns only the list of parts that are currently available. for a complete listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products or contact your loca l sales representative. cypress maintains a worldwide network of offi ces, solution centers, manufacturer's r epresentatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices . speed (mhz) ordering code package diagram part and package type operating range 200 CY7C1354DV25-200BZI 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) industrial [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 27 of 30 package diagrams figure 9. 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) (51-85050) 51-85050-*c [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 28 of 30 figure 10. 119-ball bga (14 x 22 x 2.4 mm) (51-85115) package diagrams (continued) 51-85115 *c [+] feedback
cy7c1354dv25, cy7c1356dv25 document number: 001-48974 rev. *b page 29 of 30 figure 11. 165-ball fbga (13 x 15 x 1.4 mm) (51-85180) package diagrams (continued) [+] feedback
document number: 001-48974 rev. *b revised march 20, 2010 page 30 of 30 nobl and no bus latency are trademarks of cypress semiconductor corporation. zbt is a trademark of integrated device technology , inc. all product and company names mentioned in this document are the trademarks of their respective holders. cy7c1354dv25, cy7c1356dv25 ? cypress semiconductor corporation, 2008-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document history page document title: cy7c1354dv25/cy7c1356dv25, 9-mbit (256 k x 36/512k x 18) pipelined sram with nobl? architecture document number: 001-48974 rev. ecn no. origin of change submission date description of change ** 2594961 vkn 10/22/08 nso data sheet for tellabs *a 2746930 07/31/09 njy post to external website *b 2896565 03/20/2010 njy removed obsolet e parts from ordering information table. updated package diagram, data sheet template, and sales, solutions, and legal information section. [+] feedback

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